1. Field of the Invention
The present invention relates to protection for Metal Oxide Semiconductor (MOS) integrated circuits such as Static-Random-Access-Memory (SCRAM) and more particularly relates to protection schemes against electrostatic discharge from either human or machine handling, while minimizing effects on the circuits to which the schemes are applied.
2. Description of Related Art
Electrostatic discharge (ESD) is one of the most prevalent causes for chip failures in both chip manufacturing and field operations. ESD can occur when the charges stored in machines or the human body are discharged to the chip on contact or by static induction. FIG. 1 shows different models for ESD testing. FIG. 1A shows the test for duplicating the human body model (HBM); FIG. 1B the test for duplicating the machine model (MM), and; FIG. 1C the test for duplicating the Charged Device Model (CDM).
A human walking across synthetic carpet in 80% relative humidity can potentially induce 1.5 kV of static voltage stress. In the HBM (MIL-STD 883C; Method 3015, 1988) shown in FIG. 1A, a touch of a charged person's finger is simulated by discharging a 100-pF capacitor through a 1.5K resistor. It is important that some protection network be designed into the I/O circuits of the chip so that the ESD effect can be filtered out before its propagation to the internal logic circuit effects destruction of one or more circuit elements. In addition to human handling, contact with machines can also cause ESD stress. Since body resistance is absent, the stress can be even more severe and with higher current levels. The schematic diagram of the machine model is shown in FIG. 1B. In that model the 1.5K resistor, representing the human in line impedance, is removed and a straight short condition with a 200 pf capacitor is discharged directly through the grounded DUT (device under test).
The third model is the charged device model shown in FIG. 1C. This model is intended to illustrate the discharge of the packaged integrated circuits. The charge can be accumulated either during the chip assembly process or in the shipping tubes. The CDM ESD testers electrically charge the Device Under Test (DUT) and then discharge it to ground, thus providing the high short-duration current pulse to DUT.
Small chip size, small diameter power bussing metal runs, and limited power/ground pins present particular problems with ESD irrespective of the type of CMOS device.
Larger chips have more capacitance (more available for charge storage) and are easier to handle; the smaller the chip, the more difficult the ESD problem. Moreover, narrow power bussing metal runs means the current carrying capacity of the metal is limited (acts like a fuse) and ofttimes, a static discharge will blow (melt to short or open) the line.
Power buss size is a dependency, requiring an ESD solutions. In the same manner limited ground line area is an obvious problem, because the line cannot dissipate heat due to excess current fast enough and sometimes causes adjacent device breakdown.